1. Field of the Invention
This invention relates to digital computers with associated peripheral devices. More specifically, it relates to a circuit for the regulation of the I/O command recovery time for the peripheral devices.
2. Description of the Prior Art
Many input/output (I/O) peripheral devices impose a specific timing constraint on a digital computer system. The timing constraint is known as "I/O Command Recovery Time". This constraint specifies a minimum time between successive I/O command operations. In the prior art, "timing loops" have been implemented in software to provide this I/O command recovery time. These timing loops provided an adequate delay time if the processing speed of the computer system is in the order of 6 to 8 Mhz. With the advent of 20 Mhz and higher speed systems, these timing loops execute significantly faster resulting in an I/O command recovery time that is too short for many of the peripheral devices.
In the faster machines, the prior art method of handling the problem is to provide a "compatibility speed" that forces a high speed computer to run at a slower speed to emulate a 6 Mhz to 8 Mhz computer. This causes the computer to run slower and the potential performance is not fully utilized. This under-utilization compounds itself when running the application in a multitasking environment along with other applications. The compatibility speed will force all applications to run at the slower speed.
This invention provides an independent and operator transparent system for guaranteeing the I/O command recovery time requirement while allowing maximum execution performance of the system.